#include "t100.h"
#include "ctest.h"
#include "dw_uart.h"
#include "dw_iic.h"
#include "dw_spi.h"
#include "embARC_error.h"

/*================================================================uart=======================================*/

#define DW_UART_NUM     (2)
#define UART_0_ID  (0)
#define UART_1_ID  (1)

static void dw_uart_0_isr(void *ptr);
#define DW_UART_0_BASE   (UART0__BASE)   /*!< designware uart 0 relative baseaddr */
#define DW_UART_0_INTNO  (24)           /*!< designware uart 0 interrupt number  */

static DEV_UART dw_uart_0;              /*!< designware uart object */
static DW_UART_CTRL dw_uart_0_ctrl = {  /*!< designware uart 0 ctrl */
    0, 2000000, DW_UART_0_INTNO, (INT_HANDLER_T)dw_uart_0_isr,
    1, 1, 0
};

static void dw_uart_1_isr(void *ptr);
#define DW_UART_1_BASE   (UART0__BASE)   /*!< designware uart 0 relative baseaddr */
#define DW_UART_1_INTNO  (24)           /*!< designware uart 0 interrupt number  */

static DEV_UART dw_uart_1;              /*!< designware uart object */
static DW_UART_CTRL dw_uart_1_ctrl = {  /*!< designware uart 0 ctrl */
    0,200000, DW_UART_1_INTNO, (INT_HANDLER_T)dw_uart_1_isr,
    1, 1, 0
};



/*================================================================uart=======================================*/



/*===================================SPI SLVAE===========================================*/


/**
 * \name	Designware SPI Object ID Macros
 * @{
 */
#define DW_SPI_0_ID             0       /*!< SPI 0 id macro */
/** @} end of name */

#define DW_SPI_DEFAULT_FREQ             1000000
/**
 * @name    HSDK DesignWare SPI 0 Object Instantiation
 * @{
 */

static void dw_spi_0_isr(void *ptr);
#define DW_SPI_0_REGBASE        (SPI__BASE)             /*!< designware spi 0 relative baseaddr */
#define DW_SPI_0_INTNO          (0)                  /*!< designware spi 0 interrupt number  */
#define DW_SPI_0_CLK            (2000000)       /*!< designware spi 0 clock  */
#define DW_SPI_0_RX_SAMPLEDLY   0                               /*!< designware spi 0 RXD Sample Delay  */

#define DW_SPI_0_TX_FIFO_LEN    (32)
#define DW_SPI_0_RX_FIFO_LEN    (32)

//#define DW_SPI_0_SUPPORTED_MODE DW_SPI_MASTER_SUPPORTED

DEV_SPI dw_spi_0;                                       /*!< designware spi object */
DW_SPI_CTRL dw_spi_0_ctrl;                              /*!< designware spi 0 ctrl */

/*==============================================================================*/




/*================================================================i2c=======================================*/

#define DW_I2C_NUM 1

#define DW_I2C_0_BASE (I2C0__BASE)   /*!< designware I2C 0 relative baseaddr */
#define DW_I2C_0_INTNO (0)

static DEV_IIC dw_i2c_0;
static DW_IIC_SPKLEN da_i2c_spike = {0, 0};
static DW_IIC_CTRL dw_i2c_0_ctrl;
//static DW_IIC_CTRL dw_i2c_0_ctrl = {
//  0, 250000,DW_IIC_CAP_LOADING_100PF, DW_IIC_MASTER_SUPPORTED, 16, 16, 0x0, 1, DW_I2C_0_INTNO, (INT_HANDLER_T)dw_i2c_0_isr,
//  {1,1}, {0, 0, 0, 0, 0, 0}, };


/** designware i2c 0 interrupt rountine */
static void dw_i2c_0_isr(void *ptr)
{
    return ;
}

/** designware i2c 0 open */
static int32_t dw_i2c_0_open(uint32_t mode, uint32_t param)
{
    return dw_iic_open(&dw_i2c_0, mode, param);
}


/** designware i2c 0 close */
static int32_t dw_i2c_0_close(void)
{
    return dw_iic_close(&dw_i2c_0);
}

/** designware i2c 0 controln  */
static int32_t dw_i2c_0_control(uint32_t ctrl_cmd, void *param)
{
    return dw_iic_control(&dw_i2c_0, ctrl_cmd, param);
}

/** designware i2c 0 write  */
static int32_t dw_i2c_0_write(const void *data, uint32_t len)
{
    return dw_iic_write(&dw_i2c_0, data, len);
}

/** designware i2c 0 read  */
static int32_t dw_i2c_0_read(void *data, uint32_t len)
{
    return dw_iic_read(&dw_i2c_0, data, len);
}


/** install designware i2c 0 to system */
static void dw_i2c_0_install(void)
{
	DW_IIC_REG *i2c_abs_base = NULL;
    DEV_IIC *dw_i2c_ptr = (DEV_IIC *)&dw_i2c_0;
    DEV_IIC_INFO *dw_i2c_info_ptr = &(dw_i2c_0.iic_info);
    DW_IIC_CTRL *dw_i2c_ctrl_ptr = &dw_i2c_0_ctrl;
    DW_IIC_SCL_CNT *iic_scl_cnt_ptr = NULL;
    DW_IIC_SPKLEN *iic_spklen_ptr = NULL;

    /**
     * get absolute designware base address
     */
    i2c_abs_base = (DW_IIC_REG *)DW_I2C_0_BASE;
    dw_i2c_ctrl_ptr->dw_iic_regs = i2c_abs_base;
    dw_i2c_ctrl_ptr->ic_clkhz = 2000000; /*fpga mcu 4Mhz, i2c clk = 4M/2*/
    dw_i2c_ctrl_ptr->ic_caploading = DW_IIC_CAP_LOADING_400PF;
    dw_i2c_ctrl_ptr->support_modes = DW_IIC_MASTER_SUPPORTED;
    dw_i2c_ctrl_ptr->tx_fifo_len = 16;
    dw_i2c_ctrl_ptr->rx_fifo_len = 16;
    dw_i2c_ctrl_ptr->iic_master_code = 0x0;
    dw_i2c_ctrl_ptr->retry_cnt = 1;
    dw_i2c_ctrl_ptr->intno = DW_I2C_0_INTNO;
    dw_i2c_ctrl_ptr->dw_iic_int_handler = (INT_HANDLER_T)dw_i2c_0_isr;
    iic_scl_cnt_ptr = (DW_IIC_SCL_CNT *)&dw_i2c_ctrl_ptr->iic_scl_cnt;
    iic_scl_cnt_ptr->ss_scl_hcnt = 388; /* high clk  20us*/
    iic_scl_cnt_ptr->ss_scl_lcnt = 399; /* low clk 20us */

    iic_scl_cnt_ptr->fs_scl_hcnt = 388;
    iic_scl_cnt_ptr->fs_scl_lcnt = 399;

    iic_spklen_ptr = (DW_IIC_SPKLEN *)&dw_i2c_ctrl_ptr->iic_spklen;
    iic_spklen_ptr->fs_spklen = 5;

    /** i2c info init */
    dw_i2c_info_ptr->iic_ctrl = (void *)dw_i2c_ctrl_ptr;
    dw_i2c_info_ptr->opn_cnt = 0;
    dw_i2c_info_ptr->status = 0;
    dw_i2c_info_ptr->mode = DEV_MASTER_MODE;
    dw_i2c_info_ptr->speed_mode = IIC_SPEED_STANDARD;
    dw_i2c_info_ptr->cur_state = IIC_FREE;
    dw_i2c_info_ptr->err_state = IIC_ERR_NONE;
    dw_i2c_info_ptr->addr_mode = IIC_7BIT_ADDRESS;
    dw_i2c_info_ptr->slv_addr = 0;
    dw_i2c_info_ptr->tar_addr = 0x2f;
    dw_i2c_info_ptr->next_cond = IIC_MODE_STOP;


    dw_i2c_ptr->iic_open = dw_i2c_0_open;
    dw_i2c_ptr->iic_close = dw_i2c_0_close;
    dw_i2c_ptr->iic_control = dw_i2c_0_control;
    dw_i2c_ptr->iic_write = dw_i2c_0_write;
    dw_i2c_ptr->iic_read = dw_i2c_0_read;
}




/*================================================================i2c=======================================*/



/** designware uart 0 open */
static int32_t dw_uart_0_open(uint32_t baud)
{
    return dw_uart_open(&dw_uart_0, baud);
}
/** designware uart 0 close */
static int32_t dw_uart_0_close(void)
{
    return dw_uart_close(&dw_uart_0);
}
/** designware uart 0 control */
static int32_t dw_uart_0_control(uint32_t ctrl_cmd, void *param)
{
    return dw_uart_control(&dw_uart_0, ctrl_cmd, param);
}
/** designware uart 0 write */
int32_t dw_uart_0_write(const void *data, uint32_t len)
{
    return dw_uart_write(&dw_uart_0, data, len);
}
/** designware uart 0 close */
static int32_t dw_uart_0_read(void *data, uint32_t len)
{
    return dw_uart_read(&dw_uart_0, data, len);
}
/** designware uart 0 interrupt rountine */
static void dw_uart_0_isr(void *ptr)
{
    dw_uart_isr(&dw_uart_0, ptr);
}
/** install designware uart 0 to system */
static void dw_uart_0_install(void)
{
    uint32_t uart_abs_base = 0;
    DEV_UART *dw_uart_ptr = &dw_uart_0;
    DEV_UART_INFO *dw_uart_info_ptr = &(dw_uart_0.uart_info);
    DW_UART_CTRL *dw_uart_ctrl_ptr = &dw_uart_0_ctrl;

    /**
     * get absolute designware base address
     */
    uart_abs_base = (uint32_t)DW_UART_0_BASE;
    dw_uart_ctrl_ptr->dw_uart_regbase = uart_abs_base;

    /** uart info init */
    dw_uart_info_ptr->uart_ctrl = (void *)dw_uart_ctrl_ptr;
    dw_uart_info_ptr->opn_cnt = 0;
    dw_uart_info_ptr->status = 0;
    dw_uart_info_ptr->baudrate = UART_BAUDRATE_9600;  /* default 9600bps */

    /** uart dev init */
    dw_uart_ptr->uart_open = dw_uart_0_open;
    dw_uart_ptr->uart_close = dw_uart_0_close;
    dw_uart_ptr->uart_control = dw_uart_0_control;
    dw_uart_ptr->uart_write = dw_uart_0_write;
    dw_uart_ptr->uart_read = dw_uart_0_read;
}


/** designware uart 0 open */
static int32_t dw_uart_1_open(uint32_t baud)
{
    return dw_uart_open(&dw_uart_1, baud);
}
/** designware uart 0 close */
static int32_t dw_uart_1_close(void)
{
    return dw_uart_close(&dw_uart_1);
}
/** designware uart 0 control */
static int32_t dw_uart_1_control(uint32_t ctrl_cmd, void *param)
{
    return dw_uart_control(&dw_uart_1, ctrl_cmd, param);
}
/** designware uart 0 write */
static int32_t dw_uart_1_write(const void *data, uint32_t len)
{
    return dw_uart_write(&dw_uart_1, data, len);
}
/** designware uart 0 close */
static int32_t dw_uart_1_read(void *data, uint32_t len)
{
    return dw_uart_read(&dw_uart_1, data, len);
}
/** designware uart 0 interrupt rountine */
static void dw_uart_1_isr(void *ptr)
{
    dw_uart_isr(&dw_uart_1, ptr);
}
/** install designware uart 0 to system */
static void dw_uart_1_install(void)
{
    uint32_t uart_abs_base = 0;
    DEV_UART *dw_uart_ptr = &dw_uart_1;
    DEV_UART_INFO *dw_uart_info_ptr = &(dw_uart_1.uart_info);
    DW_UART_CTRL *dw_uart_ctrl_ptr = &dw_uart_1_ctrl;

    /**
     * get absolute designware base address
     */
    uart_abs_base = (uint32_t)DW_UART_1_BASE;
    dw_uart_ctrl_ptr->dw_uart_regbase = uart_abs_base;

    /** uart info init */
    dw_uart_info_ptr->uart_ctrl = (void *)dw_uart_ctrl_ptr;
    dw_uart_info_ptr->opn_cnt = 0;
    dw_uart_info_ptr->status = 0;
    dw_uart_info_ptr->baudrate = UART_BAUDRATE_115200;  /* default 115200bps */

    /** uart dev init */
    dw_uart_ptr->uart_open = dw_uart_1_open;
    dw_uart_ptr->uart_close = dw_uart_1_close;
    dw_uart_ptr->uart_control = dw_uart_1_control;
    dw_uart_ptr->uart_write = dw_uart_1_write;
    dw_uart_ptr->uart_read = dw_uart_1_read;
}

/** get one uart device structure */
DEV_UART_PTR uart_get_dev(int32_t uart_id)
{
    switch (uart_id) {
    case UART_0_ID:
        dw_uart_0_install();
        return &dw_uart_0;
        break;
    case UART_1_ID:
        dw_uart_1_install();
        return &dw_uart_1;
        break;
    default:
    break;
    }
    return NULL;
}




/*===================================SPI SLVAE===========================================*/


/** designware spi 0 open */
static int32_t dw_spi_0_open(uint32_t mode, uint32_t param)
{
    return dw_spi_open(&dw_spi_0, mode, param);
}
/** designware spi 0 close */
static int32_t dw_spi_0_close(void)
{
    return dw_spi_close(&dw_spi_0);
}
/** designware spi 0 control */
static int32_t dw_spi_0_control(uint32_t ctrl_cmd, void *param)
{
//    switch (ctrl_cmd) {
//    case SPI_CMD_MST_SEL_DEV:
//        creg_hsdc_set_spi_cs_ctrl((CREG_HSDC_STRUCT_PTR)(HSDC_CREG_REGBASE), \
//                      CREG_HSDC_SPISEL_0, (CREG_HSDC_SPICSSEL_T)param, CREG_HSDC_SPICSCTRL_CSBYCREGVALUE0);
//        break;
//    case SPI_CMD_MST_DSEL_DEV:
//        creg_hsdc_set_spi_cs_ctrl((CREG_HSDC_STRUCT_PTR)(HSDC_CREG_REGBASE), \
//                      CREG_HSDC_SPISEL_0, (CREG_HSDC_SPICSSEL_T)param, CREG_HSDC_SPICSCTRL_CSBYCREGVALUE1);
//        break;
//    }
    return dw_spi_control(&dw_spi_0, ctrl_cmd, param);
}
/** designware spi 0 write */
static int32_t dw_spi_0_write(const void *data, uint32_t len)
{
    return dw_spi_write(&dw_spi_0, data, len);
}
/** designware spi 0 close */
static int32_t dw_spi_0_read(void *data, uint32_t len)
{
    return dw_spi_read(&dw_spi_0, data, len);
}
/** designware spi 0 interrupt routine */
static void dw_spi_0_isr(void *ptr)
{
    dw_spi_isr(&dw_spi_0, ptr);
}
/** install designware spi 0 to system */
static void dw_spi_0_install(void)
{
    uint32_t spi_abs_base = 0;
    DEV_SPI *dw_spi_ptr = &dw_spi_0;
    DEV_SPI_INFO *dw_spi_info_ptr = &(dw_spi_0.spi_info);
    DW_SPI_CTRL *dw_spi_ctrl_ptr = &dw_spi_0_ctrl;
    DW_SPI_REG *dw_spi_reg_ptr;

    /**
     * get absolute designware base address
     */
    spi_abs_base = DW_SPI_0_REGBASE;

    dw_spi_reg_ptr = (DW_SPI_REG *)spi_abs_base;

    /** spi info init */
    dw_spi_info_ptr->spi_ctrl = (void *)dw_spi_ctrl_ptr;
    dw_spi_info_ptr->status = DEV_DISABLED;
    //dw_spi_info_ptr->freq = DW_SPI_DEFAULT_FREQ;
    dw_spi_info_ptr->opn_cnt = 0;
    dw_spi_info_ptr->mode = DEV_SLAVE_MODE;
    dw_spi_info_ptr->clk_mode = SPI_CLK_MODE_DEFAULT;
    dw_spi_info_ptr->slave = SPI_SLAVE_NOT_SELECTED;
    dw_spi_info_ptr->dfs = SPI_DFS_DEFAULT;
    dw_spi_info_ptr->dummy = 0xff;

    /* spi ctrl init */
    /* Variables which should be set during object implementation */
    dw_spi_ctrl_ptr->dw_spi_regs = dw_spi_reg_ptr;
    dw_spi_ctrl_ptr->intno = DW_SPI_0_INTNO;
    dw_spi_ctrl_ptr->support_modes = DW_SPI_SLAVE_SUPPORTED;
    dw_spi_ctrl_ptr->tx_fifo_len = DW_SPI_0_TX_FIFO_LEN;
    dw_spi_ctrl_ptr->rx_fifo_len = DW_SPI_0_TX_FIFO_LEN;
    dw_spi_ctrl_ptr->dw_apb_bus_freq = DW_SPI_0_CLK;
    dw_spi_ctrl_ptr->rx_sampledly = DW_SPI_0_RX_SAMPLEDLY;
    dw_spi_ctrl_ptr->dw_spi_int_handler = dw_spi_0_isr;
    /* Variables which always change during spi operation */
    dw_spi_ctrl_ptr->int_status = 0;

    /** spi dev init */
    dw_spi_ptr->spi_open = dw_spi_0_open;
    dw_spi_ptr->spi_close = dw_spi_0_close;
    dw_spi_ptr->spi_control = dw_spi_0_control;
    dw_spi_ptr->spi_write = dw_spi_0_write;
    dw_spi_ptr->spi_read = dw_spi_0_read;
}
/** @} end of name */


/**
 * @brief    install all spi objects
 * @note    @b MUST be called during system init
 */
void dw_spi_all_install(void)
{
    dw_spi_0_install();
}

/** get one designware device structure */
DEV_SPI_PTR spi_get_dev(int32_t spi_id)
{
    static uint32_t install_flag = 0;

    /* install device objects */
    if (install_flag == 0) {
        install_flag = 1;
        dw_spi_all_install();
    }

    switch (spi_id) {

    case DW_SPI_0_ID:
        return &dw_spi_0;
        break;

    default:
        break;
    }
    return NULL;
}

/*==============================================================================*/













//============================================================================//
//===========================TEST BEGIN=======================================//
//============================================================================//



void main(void)
{
    DEV_UART *uart_dev;

    //memset((void *)(SRAM__BASE + 1024 * 500), 0xa5, 10);
    volatile unsigned int *data = (volatile unsigned int *)0x102000;
    *data = 1234;
//    const char eeprom_write_cmd[2] = {0xA0, 0xA5};

//    volatile unsigned int *uart_mcr = (volatile unsigned int *)0x802010;
//    volatile unsigned int *uart_lcr = (volatile unsigned int *)0x80200c;
//    volatile unsigned int *uart_dll = (volatile unsigned int *)0x802000;
//    volatile unsigned int *uart_dlh = (volatile unsigned int *)0x802004;
//    volatile unsigned int *uart_fcr = (volatile unsigned int *)0x802008;
//    volatile unsigned int *uart_thr = (volatile unsigned int *)0x802000;
//    volatile unsigned int *uart_ier = (volatile unsigned int *)0x802004;
//    volatile unsigned int *uart_dlf = (volatile unsigned int *)0x8020c0;
//
//    *uart_mcr = 0x23;
//    *uart_lcr = 0xa2;
//    *uart_dll = 0x22;
//    *uart_dlh = 0x00;
//    *uart_dlf = 0x0c;
//    *uart_lcr = 0x22;
//    *uart_mcr = 0xa3;
//    *uart_fcr = 0xf1;
//    *uart_ier = 0x01;
//    *uart_thr = 0x7A;
    volatile unsigned int *iomux_gpio_unlock = (volatile unsigned int *)0x80a000;
    volatile unsigned int *iomux_gpio_00_to_uart0_tx = (volatile unsigned int *)0x80a004;
    volatile unsigned int *iomux_gpio_00_to_uart0_rx = (volatile unsigned int *)0x80a008;
    volatile unsigned int *iomux_gpio_04_to_spi_clk = (volatile unsigned int *)0x80a014;
    volatile unsigned int *iomux_gpio_06_to_spi_txd = (volatile unsigned int *)0x80a01c;
    volatile unsigned int *iomux_gpio_07_to_spi_rxd = (volatile unsigned int *)0x80a020;

    volatile unsigned int *iomux_gpio_08_to_i2c1_scl = (volatile unsigned int *)0x80a024;
    volatile unsigned int *iomux_gpio_09_to_i2c1_sda = (volatile unsigned int *)0x80a028;
    char *prt_str = "T100 uart start hello world uart test printf test_uart t100_cv_bin uart test 1\n";
    char *prt_str1 = "i2c init ok\n";

    *iomux_gpio_unlock = 0x5a5a5a5a;
    *iomux_gpio_00_to_uart0_tx = 0x1;
    *iomux_gpio_00_to_uart0_rx = 0x1;
    *iomux_gpio_08_to_i2c1_scl = 0x1;
	*iomux_gpio_09_to_i2c1_sda = 0x1;
	*iomux_gpio_04_to_spi_clk = 0x1;
	*iomux_gpio_06_to_spi_txd = 0x1;
	*iomux_gpio_07_to_spi_rxd = 0x1;

    uart_dev = uart_get_dev(UART_0_ID);

    dw_uart_open(uart_dev, 9600);
    dw_uart_write(uart_dev, (const void *)prt_str, strlen(prt_str));


        volatile unsigned int *i2c0_ic_enable = (volatile unsigned int *)0x80506c;
        volatile unsigned int *i2c0_ic_con = (volatile unsigned int *)0x805000;
        volatile unsigned int *i2c0_ic_tar = (volatile unsigned int *)0x805004;
        volatile unsigned int *i2c0_ic_scl_hcnt = (volatile unsigned int *)0x805014;
        volatile unsigned int *i2c0_ic_scl_lcnt = (volatile unsigned int *)0x805018;
        volatile unsigned int *i2c0_intr_mask = (volatile unsigned int *)0x805030;
        volatile unsigned int *i2c0_rx_tl = (volatile unsigned int *)0x805038;
        volatile unsigned int *i2c0_tx_tl = (volatile unsigned int *)0x80503c;
        volatile unsigned int *i2c0_data_cmd = (volatile unsigned int *)0x805010;
        int time_out = 1000;
        int count = 0;

        *i2c0_ic_enable = 0x0;
        *i2c0_ic_con = 0x63;
        *i2c0_ic_tar = 0x2f;
        *i2c0_ic_scl_hcnt = 2488;
        *i2c0_ic_scl_lcnt = 2499;
        *i2c0_intr_mask = 0xfff;
        *i2c0_rx_tl = 0x0;
        *i2c0_tx_tl = 0x0;
        *i2c0_ic_enable = 0x1;

        *i2c0_data_cmd = 0x02;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x03;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x04;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x05;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x06;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x07;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x07;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x09;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x09;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x09;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x09;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x19;
        for (count = 0; count < time_out; count++);
        *i2c0_data_cmd = 0x29;

//    dw_i2c_0_install();
//    dw_i2c_0_open(DEV_MASTER_MODE, IIC_SPEED_STANDARD);
//    dw_i2c_0_control(IIC_CMD_ENA_DEV, NULL);
//    dw_i2c_0_write((const void *)&eeprom_write_cmd[0], 2);
//    dw_i2c_0_control(IIC_CMD_DIS_DEV, NULL);
//    dw_uart_write(uart_dev, (const void *)prt_str1, strlen(prt_str1));

//    dw_spi_0_install();
//    dw_spi_0_open(DEV_SLAVE_MODE, SPI_CPOL_0_CPHA_0);
//    dw_spi_0_write((const void *)&eeprom_write_cmd[0], 2);
}




//CTEST(uart0, bardrate_115200)
//{
//    DEV_UART *uart_dev;
//
//    uart_dev = uart_get_dev(UART_0_ID);
//
//
//
////    ASSERT_NOT_EQUAL_U(uart_dev, NULL);
//
//    ASSERT_EQUAL(dw_uart_open(uart_dev, 115200), E_OPNED);
//
//    ASSERT_EQUAL(dw_uart_write(uart_dev, "T100 uart start\n", 16), E_OK);
//}
//
//
//CTEST(uart0, bardrate_9600)
//{
//    DEV_UART *uart_dev;
//
//    uart_dev = uart_get_dev(UART_0_ID);
//
////    ASSERT_NOT_EQUAL_U(uart_dev, NULL);
//
//    ASSERT_EQUAL(dw_uart_open(uart_dev, 9600), E_OPNED);
//
//    ASSERT_EQUAL(dw_uart_write(uart_dev, "T100 uart start\n", 16), E_OK);
//}



























